Publications

2022

• S. Chatterjee and P. Zielinski. On the Generalization Mystery in Deep Learning. ArXiv preprint.

2021

• S. Rai, W. Lau Neto, Y. Miyasaka, X. Zhang, M. Yu, Q. Yi, M. Fujita, G. B. Manske, M. F. Pontes, L. S. da Rosa, M. S. de Aguiar, P. F. Butzen, P. C. Chien, Y. S. Huang, H. R. Wang, J. H. R. Jiang, J. Gu, Z. Zhao, Z. Jiang, D. Z. Pan, B. A. de Abreu, I. S. Campos, A. Berndt, C. Meinhardt, J. T. Carvalho, M. Grellert, S. Bampi, A. Lohana, A. Kumar, W. Zeng, A. Davoodi, R. O. Topaloglu, Y. Zhou, J. Dotzel, Y. Zhang, H. Wang, Z. Zhang, V. Tenace, P. E. Gaillardon, A. Mishchenko and S. Chatterjee. Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. In Proc. of DATE ‘21, pp. 1026-1031 (Invited Paper).

2020

• S. Chatterjee and A. Mishchenko. Circuit-based Intrinsic Methods to Detect Overfitting. In Proc. of ICML ‘20, pp. 1459-1468.

• S. Chatterjee. Coherent Gradients: An Approach to Understanding Generalization in Gradient Descent-based Optimization. In ICLR ‘20.

2018

• S. Chatterjee. Learning and Memorization. In Proc. ICML ‘18, pp.755-763.

2012

• S. Chatterjee, M. Kishinevsky and U.Y. Ogras. Quick Formal Modeling of Communication Fabrics to Enable Verification. In IEEE Design and Test of Computers, vol. 29(3), June 2012, pp. 80-88.

• S. Chatterjee and M. Kishinevsky. Automatic Generation of Inductive Invariants from High-Level Microarchitectural Models of Communication Fabrics. In Formal Methods in System Design, vol. 40(2), April 2012, pp. 147-169.

2011

• C.-L. Chou, R. Marculescu, U.Y. Ogras, S. Chatterjee, M. Kishinevsky and D. Loukianov. System interconnect design exploration for embedded MPSoCs. In Proc. SLIP ‘11, pp. 1-8.

• A. Gotmanov, S. Chatterjee and M. Kishinevsky. Verifying Deadlock-Freedom of Communication Fabrics. In Proc. VMCAI ‘11, pp. 214-231.

2010

• S. Chatterjee and M. Kishinevsky. Automatic Generation of Inductive Invariants from High-Level Microarchitectural Models of Communication Fabrics. In Proc. CAV ‘10, pp. 321-338. Superseded by 2012 journal version.

• S. Chatterjee, M. Kishinevsky and U.Y. Ogras. Quick Formal Modeling of Communication Fabrics to Enable Verification. In Proc. HLDVT ‘10, pp. 42-49. Superseded by 2012 journal version.

• N. Nikitin, S. Chatterjee, J. Cortadella, M. Kishinevsky, U.Y. Ogras. Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing. In Proc. NOCS ‘10, pp. 125-134.

2008

• A. Mishchenko, S. Chatterjee, R. Brayton. Boolean factoring and decomposition in logic networks. In Proc. ICCAD ‘08, pp. 38-44.

2007

• A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton. Combinational and sequential mapping with priority cuts.</a> In Proc. ICCAD ‘07, pp. 354-361.

• S. Chatterjee. On Algorithms for Technology Mapping. PhD Thesis, University of California at Berkeley, 2007.

• S. Chatterjee, A. Mishchenko, R. Brayton, and A. Kuehlmann. On resolution proofs for combinational equivalence. In Proc. DAC ‘07, pp. 600-605.

• S. Chatterjee, Z. Wei, A. Mishchenko, and R. Brayton. A linear time algorithm for optimum tree placement. In Proc. IWLS ‘07, pp. 336-342.

• A. Mishchenko, S. Chatterjee, and R. Brayton. Improvements to technology mapping for LUT-based FPGAs. In IEEE TCAD, vol. 26(2), Feb 2007, pp. 240-253.

2006

• S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam. Reducing structural bias in technology mapping. In IEEE Trans. CAD, vol. 25(12), December 2006, pp. 2894-2903.

• S. Chatterjee, A. Mishchenko, and R. Brayton. Factor cuts. In Proc. ICCAD ‘06, pp. 143-150.

• A. Mishchenko, S. Chatterjee, R. Brayton, and N. Een. Improvements to combinational equivalence checking. In Proc. ICCAD ‘06, pp. 836-843.

• A. Mishchenko, S. Chatterjee, and R. Brayton. DAG-aware AIG rewriting: A fresh look at combinational logic synthesis. In Proc. DAC ‘06, pp. 532-536.

• A. Mishchenko, S. Chatterjee, and R. Brayton. Improvements to technology mapping for LUT-based FPGAs. In Proc. FPGA ‘06, pp. 41-49.

2005

• S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam. Reducing structural bias in technology mapping. In Proc. ICCAD ‘05, pp. 518-525.

2004

• S. Chatterjee and R. Brayton. A new incremental placement algorithm and its application to congestion-aware divisor extraction. In Proc. ICCAD ‘04, pp. 541-548.